Conventional electrically programmable read-only memory (EPROM) types of cells typically have control gates that overlie the top or the top and sides of floating gates. When a control gate overlies only the top of the floating gate member, the capacitive coupling between the floating gate member and control gate member typically does not exceed about 50% of the total floating gate capacitance (i.e., capacitance ratio=50%). When a control gate lies adjacent to the top and sides of the floating gate, the capacitive coupling ratio may increase to about 70%.
An attempt to increase capacitive coupling ratio may include the use of a control gate that lies adjacent to the top, sides, and part of the bottom of a T-shaped floating gate. The formation of this type of device is complex and may include two deposition steps and two patterning steps. Further, the intergate dielectric layer (between the control gate and the floating gate) may include two distinct regions, and its formation may require three steps. For example, one region may be between the bottom of the floating gate and an underlying portion of the control gate, and the other region may be between the top of the floating gate and an overlying portion of the control gate. Extra processing steps typically lower yield, raise substrate cost, increase cycle time, and are generally undesired.